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CHIPS Articles: DARPA Pursues Scalable On-Chip Cybersecurity

DARPA Pursues Scalable On-Chip Cybersecurity
By CHIPS Magazine - April 1, 2019
For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way toward the underlying hardware. At the same time, popular rise of the internet of things (IoT) has driven the creation of a rapidly growing number of accessible interconnected devices and a host of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications, DARPA warned in a release. The harsh consequences of a hardware cyberattack are significant because a compromise could potentially impact not millions, but billions of devices.

Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design, DARPA said.

Interestingly, integrating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. Further complicating this stalemate is that the inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance and power dissipation. In addition, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible.

“Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA’s Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today’s chips largely unprotected.”

To facilitate the development of secure chips, DARPA initiated the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity, DARPA explained.

To overcome all the obstacles in designing a scalable, secure chip, DARPA aims to develop a design tool and IP ecosystem, which includes tool vendors, chip developers, IP licensers, and the open source community, that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise?ultimately making scalable on-chip security ubiquitous across manufacturers.

“The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today’s manual processes it’s hard to determine where tradeoffs can be made,” Leef said.

DARPA’s AISS program aims to create a novel, automated chip design flow that will allow the security mechanisms to well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased, DARPA said.

While the threat landscape is ever evolving and perpetrators are inexhaustible, AISS will attempt to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include: side channel attacks; reverse engineering attacks; supply chain attacks; and malicious hardware attacks.

“Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” Leef said.

In addition to incorporating scalable defense mechanisms, AISS wants to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. “To this end, the program will also aim to move forward provenance and integrity validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches. These techniques may include IP watermarking and threat detection to help validate the chip’s integrity and IP provenance throughout its lifetime,” DARPA stated.

AISS is part of the second phase of DARPA’s Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security.

DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers. For details about the event, including registration requirements, please see here.

Additional information will be available in the forthcoming Broad Agency Announcement, which will be posted to www.fbo.gov.

The image depicts the approach expected under the AISS program. The defenses under AISS will focus on securing the inner perimeter from four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. The on-chip security engine AISS seeks to develop will aid designers in assessing which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise. DARPA image
The image depicts the approach expected under the AISS program. The defenses under AISS will focus on securing the inner perimeter from four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. The on-chip security engine AISS seeks to develop will aid designers in assessing which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise. DARPA image
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